Espressif Systems /ESP32-S2 /RMT /CH1CONF1

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Interpret as CH1CONF1

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TX_START)TX_START 0 (RX_EN)RX_EN 0 (MEM_WR_RST)MEM_WR_RST 0 (MEM_RD_RST)MEM_RD_RST 0 (APB_MEM_RST)APB_MEM_RST 0 (MEM_OWNER)MEM_OWNER 0 (TX_CONTI_MODE)TX_CONTI_MODE 0 (RX_FILTER_EN)RX_FILTER_EN 0RX_FILTER_THRES0 (CHK_RX_CARRIER_EN)CHK_RX_CARRIER_EN 0 (REF_ALWAYS_ON)REF_ALWAYS_ON 0 (IDLE_OUT_LV)IDLE_OUT_LV 0 (IDLE_OUT_EN)IDLE_OUT_EN 0 (TX_STOP)TX_STOP

Description

Channel 1 configure register 1

Fields

TX_START

Set this bit to start sending data on CHANNEL%s.

RX_EN

Set this bit to enable receiver to receive data on CHANNEL%s.

MEM_WR_RST

Set this bit to reset write ram address for CHANNEL%s by accessing receiver.

MEM_RD_RST

Set this bit to reset read ram address for CHANNEL%s by accessing transmitter.

APB_MEM_RST

Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo.

MEM_OWNER

This register marks the ownership of CHANNEL%s’s ram block.

1’h1: Receiver is using the ram.

1’h0: Transmitter is using the ram.

TX_CONTI_MODE

Set this bit to restart transmission from the first data to the last data in CHANNEL%s.

RX_FILTER_EN

This is the receive filter’s enable bit for CHANNEL%s.

RX_FILTER_THRES

Ignores the input pulse when its width is smaller than this register value in APB clock periods (in receive mode).

CHK_RX_CARRIER_EN

Set this bit to enable memory loop read mode when carrier modulation is enabled for channel %s.

REF_ALWAYS_ON

This bit is used to select the base clock for CHANNEL%s.

1’h1: clk_apb 1’h0:clk_ref

IDLE_OUT_LV

This bit configures the level of output signal in CHANNEL%s when the latter is in IDLE state.

IDLE_OUT_EN

This is the output enable-control bit for CHANNEL%s in IDLE state.

TX_STOP

Set this bit to stop the transmitter of CHANNEL%s sending data out.

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